Matrix multiplication is most often involved in graphics, image processing, digital signal processing, robotics and control engineering applications. In this paper we compared and analyzed the power and energy consumption in three different designs, which multiply two matrices A and B of nxn 32-bit items and store the result in C matrix of nxn 64-bit items. The first two designs use FPGA HW with different number of storage registers 2n and 2n2 and the third design uses a computer system piloted by NIOS II\e processor with On-Chip memory. We showed that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multiplier on FPGA. Since our target FPGA is the Altera cyclone II family, we also had to find one acceptable method to measure the real power consumption in the FPGA device.
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机译：矩阵乘法最经常涉及图形，图像处理，数字信号处理，机器人技术和控制工程应用。在本文中，我们比较并分析了三种不同设计的功耗和能耗，这三种设计将nxn个32位项目的两个矩阵A和B相乘，并将结果存储在nxn 64位项目的C矩阵中。前两种设计使用具有不同数量的存储寄存器2n和2n2的FPGA硬件，第三种设计使用由NIOS II \ e处理器控制的计算机系统，并带有片上存储器。我们证明，与FPGA上的硬件矩阵乘法器相比，NIOS II \ e不是乘以nxn矩阵的节能替代方案。由于我们的目标FPGA是Altera Cyclone II系列，我们还必须找到一种可接受的方法来测量FPGA器件中的实际功耗。
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